As the semiconductor industry has strived for higher device density, higher performance, and lower costs, problems involving both fabrication and design have been encountered. One solution to these problems has been the development of a fin-like field effect transistor (FinFET). A typical FinFET includes a thin vertical ‘fin’ formed by etching spaced recesses into a substrate. The source, drain, and channel regions are defined within this fin. The transistor's gate is wrapped around the channel region of the fin, engaging it on both the top of the fin and the sides of the fin. This configuration allows the gate to induce current flow in the channel from three sides. Thus, FinFET devices have the benefit of higher current flow and reduced short-channel effects.
The dimensions of FinFETs and other metal oxide semiconductor field effect transistors (MOSFETs) have been progressively reduced as technological advances have been made in integrated circuit materials. For example, high-k metal gate (HKMG) processes have been applied to FinFETs. However, HKMG devices often require multiple layers in the gate structure. For example, a plurality of layers may be used to tune the work function values of the metal gates. Although these approaches have been adequate for their intended purpose, they have not been satisfactory in all respects. For example, materials currently used as work function layers very often impart high resistivity to the gate stack. In short-channel devices in particular, gate resistance may degrade performance because the work function layer may constitute the bulk of the metal gate electrode, or even the entire metal gate electrode.